Showing posts with label rgpv m.tech vlsi design syllabus. Show all posts
Showing posts with label rgpv m.tech vlsi design syllabus. Show all posts

Friday, 20 August 2010

VLSI TECHNOLOGY (MEVD-201)

META TAGS:-RGPV VLSI DESIGN 2ND SEM SYLLABUS I RGTU VLSI DESIGN M.TECH SYLLABUS I RGPV M.TECH VLSI DESIGN SYLLABUS I RGTU M.E. VLSI DESIGN SYLLABUS I RGPV M.TECH MICRO ELECTRONICS AND VLSI DESIGN SYLLABUS I RGPV M.TECH VLSI DESIGN  VLSI TECHNOLOGY SYLLABUS I M.TECH VLSI DESIGN SYLLABUS I VLSI TECHNOLOGY SYLLABUS I M.TECH 2ND SEM VLSI TECHNOLOGY SYLLABUS I RGTU M.TECH 2ND SEM VLSI TECHNOLOGY SYLLABUS
Rajiv Gandhi Technological University, Bhopal (MP)
M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)
MEVD – 201 VLSI TECHNOLOGY
UNIT  I
Overview of Semiconductor Processing:Electronic grade silicon preparation,Crystal growth,Czochralski process,wafer-preparation ,slicing,Marking, polishing,evaluation. Basic wafer fabrication operations,wafer sort,clean room construction and maintenance.

UNIT II
Oxidation:Objectives,Silicon dioxide layer uses,Thermal oxidation mechanism and methods, Kinetics of oxidation,Deal Grove model,Oxidation processes,post oxidation evaluation.

UNIT III
Basic Patterning: Overview of Photo-masking process, Ten step process, Basic photoresist chemistry, comparison of positive and negative photoresists, X-ray lithography, Electron beam exposure system.

UNIT IV
Doping:Definition of a junction, Formation of doped region and junction by diffusion, diffusion process steps,deposition,drive-in-oxidation,Ion implantation -concept and system, implant damage,Comparison of diffusion and ion-implantation techniques.

UNIT V
Deposition:Chemical Vapor Deposition (CVD), CVD Process steps,CVD System types, Low- Pressure CVD (LPCVD),Plasma-enhanced CVD (PECVD),Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Metalorganic CVD (MOCVD),SOS (Silicon on Sapphire) and SOI (silicon on Insulator).Brief Introduction to Metallization.

TEXT / REFERENCE BOOKS:
  • S.M. Sze, VLSI Technology, McGraw-Hill, 2nd Ed.
  • S. K. Gandhi, VLSI Fabrication Principles, Wiley
  • W. R. Runyan, Silicon Semiconductor Technology, McGraw-Hill.

Thursday, 19 August 2010

CMOS VLSI DESIGN SYLLABUS

TAGS:- RGTU M TECH SYLLABUS, RGPV CMOS VLSI SYLLABUS, M TECH VLSI DESIGN SYLLABUS,RGPV  M.TECH 1ST SEM SYLLABUS, RGPV M.TECH 1ST SEM VLSI DESIGN SYLLABUS, CMOS VLSI DESIGN M.TECH SYLLABUS, RGPV ECE M TECH SYLLABUS, DOWNLOAD M.TECH 1ST SEM SYLLABUS  I RGPV M.TECH CMOS VLSI DESIGN SYLLABUS I RGTU CMOS VLSI DESIGN M.TECH SYLLABUS I RGTU M.TECH CMOS DESIGN SYLLABUS I RGPV CMOS DESIGN SYLLABUS
Rajiv Gandhi Technological University, Bhopal (MP)
M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

CMOS VLSI DESIGN SYLLABUS
UNIT-I
VLSI design methodologies:VLSI Design flow, Design Hierarchy, Regularity, Modularity and Locality,VLSI design styles,Design quality,Packaging technology.MOS device design equations , Second order effects, the complementary CMOS Inverter DC characteristics.

UNI-II
Circuit Characterization and Performance Estimation:Parasitic effect in Integrated Circuits ,Resistance estimation,capacitance estimation,Inductance.Switching characteristics,CMOS - Gate transistor sizing,Power dissipation,CMOS Logic Structures,Clocking Strategies.
 
UNITIII
CMOS Process Enhancement & Layout Considerations:Interconnect,circuit elements, Stick diagram, Layout design rules, Latchup, latchup triggering, latchup prevention, Technology related CAD issues.
 
UNIT IV
Subsystem Design: Structured design of combinational logic-parity generator,Multiplexer, code converters.Clocked sequential circuits-two phase clocking,charge storage,dynamic register element,dynamic shift register. Subsystem design process,Design of ALU subsystem, Adders, Multipliers.Commonly used storage/ memory elements.
 
UNIT V
Field Programmable Devices:Definitions of Relevant Terminology,Evolution of Programmable Logic Devices,User-Programmable Switch Technologies,Computer Aided Design (CAD) Flow for FPDs,Programmable Logic,Programmable Logic Structures,Programmable Interconnect, Reprogrammable Gate Array, Commercially Available SPLDs,CPLDs and FPGAs,Gate Array Design,Sea-of-Gates.
 
TEXT / REFERENCE BOOKS:
  • D.A. Pucknell, K. Eshraghian, Basic VLSI Design, PHI, 3rd Ed.
  • John P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons.
  • Niel H.E. Weste, K. Eshraghian,, Principles of CMOS VLSI Design, Person, 2nd Ed.
  • Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley.
  • A. Mukherjee, Introduction to nMOS and CMOS VLSI systems design, Prentice Hall.